As more compact, thinner mobile devices with more functions have been developed, the overall thicknesses of such devices are required to be thinner. A solution that has been proposed to meet the demand is a printed wiring board with a built-in semiconductor element.
In a conventional printed wiring board with a built-in semiconductor element, a wiring circuit is formed also on a sealing material to achieve high-density wiring (see Patent Document 1, for example).
Another conventional printed wiring board with a built-in semiconductor element is produced by counterboring a substrate (an organic substrate is typically used) to form a recess, mounting a semiconductor element in the recess, connecting the semiconductor element to the substrate through wire bonding, sealing the semiconductor element with a sealing material and forming a wiring layer in an overlying layer (see Patent Document 2, for example).
[Patent Document 1]: Japanese Patent Application Laid-Open Publication No. 9-46046
[Patent Document 2]: Japanese Patent Application Laid-Open Publication No. 2001-15926
However, the conventional printed wiring boards with built-in semiconductor elements have the following problems.
A first problem of the conventional printed wiring boards with built-in semiconductor elements described above will be first described with reference to FIG. 9(A). A printed wiring board 600 with a built-in semiconductor element shown in FIG. 9(A) has a configuration in which a semiconductor element 602 is connected to a base substrate 601 through wire bonding 603 and the semiconductor element 602 including the wire bonding 603 is then sealed with a sealing material 604. The sealing material 604, however, contains a large amount of inorganic fillers and a small amount of resin to balance the linear expansion coefficient of the semiconductor element 602 with those of side and overlying wiring layers 605, which are organic substrates. The sealing material 604 having such composition likely produces excessive roughness only on its surface in a desmear treatment for circuit formation. This disadvantageously reduces adhesion between the wiring circuit and the sealing material 604 when subjected to thermal history in backend production steps, often resulting in delamination. FIG. 9(B) is a cross-sectional view showing such a delaminated wiring circuit 606.
A second conventional problem in a printed wiring board 700 with an embedded semiconductor element 701 shown in FIG. 10(A) will be described. The printed wiring board 700 with a built-in semiconductor element has a configuration in which the semiconductor element 701 is mounted in a counterbored recess in an insulating substrate and connected through wire bonding 702 and the semiconductor element 701 including the wire bonding 702 is sealed with epoxy resin, which is a sealing material 703.
However, if the adjusted amount of the filled sealing material 703 is insufficient, a gap 704 will be created between the sealing material 703 and an overlying wiring layer. The gap 704 will expand due to the heat generated in a reflow process or the like when surface mounting components are mounted, disadvantageously resulting in cracking or delamination 705 of the overlying wiring board as shown in FIG. 10(B).
In addition, a third conventional problem will be described with reference to FIG. 11(A). A printed wiring board 800 with a built-in semiconductor element shown in FIG. 11(A) has a configuration in which a semiconductor element including wire bonding is sealed with a sealing material 801. However, when the amount of the filled sealing material 801 is excessive, the sealing material 801 overflows on the upper surface of a side wiring board, disadvantageously resulting in a situation where an extra polishing step is required.
In addition to the extra polishing step, since the material of the sealer differs from that of the side wiring board, it is difficult to perform polishing uniformly. Therefore, the surface of the sealing material 801 likely has irregularities 802 in a disadvantageous manner, as shown in FIG. 11(B).
If the surface filled with the sealing material 801 cannot be polished uniformly, the irregularities also affect an overlying wiring layer, so that it is difficult to form a flat overlying wiring layer. That is, the overlying wiring layer affected by the irregularities makes it difficult to form a wiring circuit with a narrow linewidth (50 μm or smaller, in particular).
Furthermore, since the sealing material 801 contains a large amount of filling material, such as inorganic fillers, there is a problem of poor adhesion to the overlying wiring board.
When the recess in which the semiconductor element is mounted is entirely covered with the sealing material 801, as mentioned above, the fact that the sealing resin contains a large amount of inorganic fillers and a small amount of resin causes a problem of deformed shapes of holes in a desmear treatment, which is carried out after the step of drilling through holes, vias and the like for interlayer connection.
The present invention has been made in view of such conventional problems described above and aims to provide a printed wiring board with a built-in semiconductor element in which a semiconductor element is built in the printed wiring board and a sealing material covers the semiconductor element to protect it from moisture absorption. The printed wiring board is characterized in that an insufficient amount of the filled sealing material does not suffer from the gap problem and an excessive amount of the filling material does not require polishing or the like in backend steps, thus exhibiting excellent adhesion to an overlying wiring board. The present invention also provides a process for producing such a printed wiring board with a built-in semiconductor element.